1. Field of the Invention
The present invention relates to a pulse signal generating apparatus and a pulse signal generating method, and more specifically, to a technique capable of producing a desired pulse signal under a program control.
2. Description of the Related Art
Conventionally, in a microcomputer application apparatus such as a video player, an audio player, various type of pulse signal generating apparatuses are used to control the operation of the apparatus. Such a pulse signal generating apparatus is well known in which a pulse signal having an, optional waveform can be generated under a program control.
FIG.1 shows a blockidiagram of one example of such a conventional pulse signal generating apparatus. This pulse signal generating apparatus is composed of a timer 50, a comparator 51 with a register (will be simply referred to as a xe2x80x9ccomparator 51xe2x80x9d hereinafter), a buffer 52, a latch 53, a port 54 and a central processing unit (will be simply referred to as a xe2x80x9cCPUxe2x80x9d hereinafter) 55. The timer 50 is composed of a counter that the content is incremented at every predetermined time interval. A timer count value outputted from this timer 50 is supplied to a comparator 51.
The comparator 51 is composed of a register and a comparator (illustrating neither). A timing data from the CPU 55 is set in the register. This timing data is used to determine a transition timing of a pulse signal to be generated. The comparator compares the timing data in the register and the timer count value outputted from the timer 50, and outputs a coincidence signal when the timing data in the register coincides with the timer count value outputted from the timer 50. The coincidence signal outputted from this comparator 51 is supplied to the buffer 52, and is also supplied to the CPU 55 as an interruption signal.
The buffer 52 stores a level data sent from the CPU 55. The level data is used to determine the level of the pulse signal to be generated in this pulse signal generating apparatus. The level data stored in this buffer 52 is transferred to the latch 53 when the coincidence signal is supplied from the comparator 51. The latch 53 holds the level data until a new level data is supplied from the buffer 52. The content of this latch 53 is send to a external device (not shown) through the port 54.
Subsequently, an operation of the conventional pulse signal generating apparatus with employment of the above-explained arrangement will now be described with reference to the explanatory diagram shown in FIG. 2.
First, the CPU 55 sets a timing data TD1 into the register included in the comparator 51 and sets xe2x80x9c1xe2x80x9d as level data into the buffer 52. In this condition, the timer 50 begins a counting operation. Then, when the data outputted from the timer 50 coincidences with the timing data TD1 stored in the comparator 51, the comparator 51 outputs an coincidence signal.
As a result, the level data of xe2x80x9c1xe2x80x9d stored in the buffer 52 is transferred to the latch 53. Through above operations, the level of the pulse signal outputted from the port 54 becomes a high level (hereinafter, is called xe2x80x9cH levelxe2x80x9d) at timing T1. Also, the coincidence signal outputted from the comparator 51 is supplied to the CPU 55 as the interruption signal. In response to this interruption signal, the CPU 55 sets a timing data TD2 in the comparator 51 and also sets level data of xe2x80x9c0xe2x80x9d in the buffer 52. In this condition, the counting operation of the timer 50 is continuously executed, and when the data outputted from the timer 50 coincidences with the timing data TD2 stored in the comparator 51, the comparator 51 outputs an coincidence signal.
As a result, the level data of xe2x80x9c0xe2x80x9d in the buffer 52 is transferred to the latch 53. Through above operations, the level of the pulse signal outputted from the port 54 becomes a low level (hereinafter, is called xe2x80x9cL levelxe2x80x9d) at timing T2. Also, the coincidence signal outputted from the comparator 51 is supplied to the CPU 55 as an interruption signal. In response to this interruption signal, the CPU 55 sets a timing data TD3 in the comparator 51 and also sets level data of xe2x80x9c1xe2x80x9d in the buffer 52. Subsequently, while operations similar to the above operations are repeatedly carried out, such a pulse signal as shown in FIG. 2 is generated.
According to this conventional pulse signal generating apparatus, because the timing data to be set in the comparator 51 and the level data to be set in the buffer 52 are suitably changed into, the pulse signal having a desired waveform (pulse width) can be generated.
As a related conventional technology, Japanese Laid Open Patent Disclosure (JP-A-Heisei 2-199503) discloses xe2x80x9cA MICROCOMPUTERxe2x80x9d. This microcomputer equips a memory which stores at least one of the program and the data, a central processing unit which executes calculation processing in accordance, with the program stored in the memory, and a pulse producing circuit which generates a pulse signal based on the data set from this central processing unit and outputs the pulse signal. The pulse producing circuit of this microcomputer equips with a counter, a comparator with a plurality of registers, a first pulse output circuit, an arbitration circuit, a second pulse output circuit and a selection circuit.
The content of the counter is renewed based on the externally supplied clock. The comparator with the plurality of registers compares the data set from the central processing unit and the content of the counter, and when the data set from the central processing unit coincidences with the content of the counter, outputs a coincidence signal. The first pulse output circuit is set/reset in response to the coincidence signal outputted from the comparator with the plurality of registers and externally outputs a first output pulse. The arbitration circuit arbitrates the coincidence signals outputted from a part of the comparator with the plurality of registers based on the fixed priority, and then outputs a reading signal for reading data to the other part of the comparator with the plurality of registers. The second pulse output circuit outputs the data read from the comparator with the registers by using the reading signal supplied from the arbitration circuit to outside as the second signal pulse. The selection circuit makes either of the first and the second pulse output circuit operate.
According to this microcomputer, when the data that defines the rising time and the falling time of each phase is stored in the comparator with the plurality of registers, the comparator with the plurality of registers compares the stored data and the content of the counter. Then, the first pulse output circuit is set/reset by the coincidence signal outputted from the comparator with the plurality of register. As a result, such a PWM pulses signal that the conventional microcomputer generates is obtained. Also, if the output timing data which shows the output time of the data is stored into a part of the comparator with the plurality of registers and data to be outputted is stored in another part of the comparator with the plurality of registers, so-called real-time processing to output desired data in the desired timing can be performed. In this case, when the same output timing data is stored in the comparator with the plurality of registers, the arbitration circuit arbitrates these timing based on predetermined priority. As a result, the conflict among the data can be prevented.
Also, Japanese Laid Open Patent Disclosure (JP-A-Heisei 8-76875) discloses xe2x80x9cMICROCOMPUTER APPLICATION SYSTEMxe2x80x9d. In this microcomputer application system, a counter is cleared when the write pulse detecting station detects a write cycle signal of the CPU. Then, the content of the counter is compared with the content of the control register at a comparator, and an idle state signal is outputted from the state detection signal output section in case of the coincidence. As a result, when the CPU is in the idle state, a current clock is switched to the half degree of the rating and is supplied to the peripheral circuits. When cash miss-hit is detected, an idle state cancellation signal is outputted from the state detection signal output section. As a consequently, the idle state is stopped, and the current clock is changed to the rating clock and is supplied to the peripheral circuit.
According to this microcomputer application system, when the CPU is in the idle state, because the peripheral circuit operates at the low clock frequency, a consumption power of the peripheral circuit can be suppressed.
Also, Japanese Laid,Open Patent Disclosure (JP-A-Heisei 9-145783) discloses xe2x80x9cIC TEST APPARATUSxe2x80x9d. This IC test apparatus is provided with a timer unit to generate a timing signal to apply the signal for the test which is sent from the tester controller to the test unit to the test head and to output the generated timing signal to the external appliance. Also, this IC test apparatus is provided with a counter,ia register and a coincidence circuit. The counter counts the timing pulse inputted into the test unit from the timer unit. The register stores the timing information that applies a signal for the test to the test head. The coincidence circuit compares the timing information stored in the register and the content of the counter and outputs the signal for the test to the test head in case of the coincidence.
According to this IC test apparatus, the producing of the signal for the test is not performed by the interruption to the CPU from the timer. As a result, the degradation of the time precision, which is caused by the software processing, and the increase of the load of the CPU are prevented.
Moreover, Japanese Patent NO. 2773546 discloses xe2x80x9cPULSE GENERATING CIRCUITxe2x80x9d. This pulse generating circuit is provided with selection means, a timer, a first comparator with a register and a second comparator with a register. The selection means selects either of an external event signal and a time signal. The timer calculates the length of the signal selected by the selection means. The first comparator with the register and the second comparator with the register store a predetermined value respectively, and compare this stored predetermined value with the count value outputted from the timer, and then output a coincidence signal when a coincidence of the predetermined value and the count value is occurred. At this pulse generating circuit, the length of the external event signal is calculated by the timer and when a coincidence of the count value in the timer with the predetermined value is occurred, an coincidence signal is outputted from the first comparator with register. The selection means select the time signal according to this coincidence signal, then the length of this time signal is calculated by the timer. This count value in the timer is compared with the predetermined value in the comparator with second register and coincidence is detected
According to this pulse generating circuit, by switching the count clock inputted to the timer based on the coincidence signal outputted from the comparator with register, the differing count clocks such as the time signal and the external event signal can be intermingled with one piece of pulse output. As a result, hardware quantity is reduced and the load of the software processing is reduced.
However, in the above mentioned conventional pulse signal occurrence apparatus, the CPU 55 must set timing data in the comparator 51 and set level data in the buffer 52 respectively every time the timing to change a waveform is arrived. As a result, when the pulse signal where much change of the output level occurs is generated, the interruption frequently occurs and the load of the CPU 55 becomes heavy. Especially, at the microcomputer for the video apparatus having a software servo function, the performance of the software servo degrades because the interruption occurs frequently.
Incidentally, according to the microcomputer disclosed in the above Japanese Laid Open Patent Disclosure (JP-A-Heisei 2-199503), the pulse signal can be generated under the programmable control. However, when the pulse signal where much change of the output level occurs is generate, the load of the CPU can not be reduced because the number of times to set data in the comparator with register must be increased like the conventional pulse signal generating apparatus shown in FIG. 1.
Also, according to the microcomputer application system disclosed in the Japanese Laid Open Patent Disclosure (JP-A-Heisei 8-76875), one of the clocks which is selected from two kinds of clocks, each of which has an different frequency each other, by whether or not the CPU is an idle state can be supplied to the peripheral circuit. However, the technique disclosed in this microcomputer application system, the optional pulse signal can not be genera ed and also the load of the CPU can not be reduced.
Also, the IC test apparatus disclosed in the Japanese Laid Open Patent Disclosure (JP-A-Heisei 9-145783) is the technique for controlling the timing to output a pulse signal but is not the technique for producing pulse signal. As a result, the optional pulse signal can not be generated.
Moreover, at the pulse generating circuit shown in the Japanese Patent NO. 2773546, like the pulse signal generating apparatus described by referring to FIG. 1, the CPU must set data in the comparator with register in response to the interruption generated every time the timing to change a pulse is arrived. Since when the pulse signal where much change of the output level occurs is generated, the interruption occurs frequently, such a problem that the load of the CPU 55 becomes heavy is not canceled.
Therefore, the present invention has an object to provide an pulse signal generating apparatus and a pulse signal generating method capable of producing a pulse signal having an optional waveform, and moreover, capable of reducing the load of the processor.
To achieve the above-described object, pulse signal generating apparatus, according to a first aspect of the present invention, includes a control circuit, a shift register, a counter and a processor. The control circuit generates a trigger signal to trigger a transition of a signal level. The shift register to which level data to define a signal level is set and in which the level data is serially shifted in response to the trigger signal from the control circuit to generate a pulse signal. The pulse signal is generated based on data shifted out from the shift register. The counter increments a content according to the trigger signal from the control circuit to generate an interruption signal every time the content reaches a predetermined value. The processor sets the level data in the shift register in response to the interruption signal from the counter.
In the pulse signal generating apparatus according to the first aspect, the control circuit includes a timer, n (n is equal to or more than 2 integer) comparators and a gating circuit. A content of the timer is incremented at every predetermined time interval. Each of the n comparators is provided with a register to store a timing data to define a transition timing of the signal level, and each comparator compares the timing data with the content of the timer to output an coincidence signal when the timing data coincides with the content of the timer. The gating circuit generates the trigger signal when the coincidence signal is generated from either of the n comparators. In this structure, the counter generates the interruption signal every time the content of the timer reaches a value of n.
Also, in this pulse signal generating apparatus, the timing data, which is set in the register, is supplied from the processor. Furthermore, the timer is composed of a programmable timer in which data to define the predetermined time interval is set from the processor.
Similarly, to achieve the above-described object, a pulse signal generating method, according to a second aspect of the present invention, includes steps of producing a trigger signal to trigger a transition of a signal level, shifting a level data to define the signal level in response to in the trigger signal serially, generating a pulse signal based on a data which is shifted out at the shifting step, incrementing a count value according to the trigger signal to generate an interruption signal every time the count value reaches a predetermined value; and initializing the level data in response to the interruption signal.
In the pulse signal generating apparatus according to the second aspect, the step of producing the trigger signal comprises the steps of incrementing a timer count value at every predetermined time interval, comparing each of n (n is equal to or more than 2 integer) timing data to define a transition timing of the signal level and the timer count value and producing the trigger signal when the timer count value coincides with either of the timing data.
Also, in this pulse signal generating method, the n timing data are supplied from a processor. Furthermore, the predetermined time interval of incrementing the timer count value is determined based on data supplied from a processor.